As known, a classical Doherty amplifier has two amplifying stages arranged in parallel and of the same power capability. The first one of the stages (main stage) operates in a class-AB amplifier mode and the second one (peak stage) operates in a class-C amplifier mode. These stages are separated at their inputs and at their outputs by 90° phase-shifting networks. The output phase-shifting network has a specific characteristic impedance Z0 which must be equal to the optimal load impedance RLm of the main stage. The input signal is split so as to drive the two amplifiers, and a summing network, known as an “impedance inverter” or a “Doherty combiner”, is operative to: a) combine the two output signals, b) to correct for phase differences between the two output signals, and c) to provide an inverted impedance at the output of the Doherty amplifier with respect to the impedance as seen from the output of the main stage.
The classical Doherty amplifier is a so-called 2-way amplifier with a main stage and a single peak stage. A multi-way (or N-way) Doherty amplifier has a main stage and a plurality of peak stages operating in parallel. An advantage of a multi-way Doherty system is that it extends the back-of level far beyond the symmetrical 2-way design without exhibiting significant drop in efficiency between the efficiency peaking points. As a result, an improvement of efficiency is possible at 12 dB power back-off, not at 6 dB back-off as for a symmetrical 2-way Doherty amplifier. The 12 dB power back-off is currently demanded by new communication systems such as 3G-LTE (third generation long-term evolution) and WiMAX (Worldwide Interoperability for Microwave Access). A classical 3-way Doherty requires quarter-wave-length lines between the outputs of the main stage and its first peak stage and also between the outputs of the first and additional peak stages. This makes the design of such a Doherty system very complicated. In addition, such design requires a large space in order to accommodate it, and mass-production samples can be predicted as showing very inconsistent behavior.
Typically, the main stage and the peak stages are implemented using a respective power transistor as each of the respective stages.